1. Technical Field
The present invention relates to an apparatus for generating an elevated voltage, and more particularly, to an apparatus for generating an elevated voltage that is capable of restricting a pumping level to a predetermined level without depending on an increase of an external supply voltage.
2. Related Art
Generally, an apparatus for generating an elevated voltage supplies a predetermined elevated voltage to circuits in the semiconductor memory that require a higher voltage than an external supply voltage. In order to compensate for a loss of a threshold voltage of transistors, the apparatus for generating an elevated voltage pumps and then uses the external supply voltage so as to have a level of an internal voltage VCORE+a threshold value Vth+an allowance value a or the internal voltage VCORE+the threshold value Vth+a substrate bias voltage |VBB|+an allowance value a.
The apparatus for generating an elevated voltage is mainly used in a word line driver, an output buffer or the like. In order that during an active operation, after a word line is selected, data is transmitted through a cell transistor without a charge loss, it is required that the apparatus for generating an elevated voltage have an elevated voltage equal to the internal voltage VCORE+the threshold value Vth+the substrate bias voltage |VBB|+the allowance value a.
FIG. 1 is a diagram illustrating a conventional elevated voltage generating apparatus.
As shown in FIG. 1, the elevated voltage generating apparatus includes a potential detecting unit 10 to which an output voltage VPP of a pumping unit 14 is fed back and which compares the output voltage of the pumping unit 14 with a prescribed voltage so as to output the comparison result DET_ENABLE; an oscillation unit 12 that is connected to the potential detecting unit 10 and outputs an oscillation signal OSC for cyclically controlling a pumping operation; and the pumping unit 14 that pumps an external supply voltage VDD in response to the pulse signal OSC outputted by the oscillation unit 12 and outputs the pumping voltage VPP.
In the elevated voltage generating apparatus shown in FIG. 1, the pumping unit 14 pumps the external supply voltage VDD in response to the pulse signal OSC outputted by the oscillation unit 12. In this case, the output voltage VPP of the pumping unit 14 is fed back to the potential detecting unit 10. When the pumping voltage level is not more than a prescribed voltage level, the oscillation unit 12 becomes enabled by the output signal DET_ENABLE of the potential detecting unit 10 and thus a pumping operation is performed. When the pumping voltage level is not less than the prescribed voltage level, the oscillation unit 12 becomes disabled by the output signal DET_ENABLE of the potential detecting unit 10 and thus a pumping operation is not performed.
FIG. 2 is a diagram illustrating an example of the pumping unit shown in FIG. 1.
As shown in FIG. 2, the conventional pumping unit 14 includes an inverter IV that is driven by a first control signal VIN1 generated by the output signal OSC of the oscillation unit 12 and that outputs an external supply voltage VDD, a first capacitor C1 that charges the external supply voltage VDD outputted by the inverter IV, a MOS transistor P1 that is connected between the first capacitor C1 and the output terminal and that is driven by a second control signal VIN2 generated by the output signal OSC of the oscillation unit 12, and a second capacitor C2 that is connected between the output terminal and a ground terminal VSS.
In this case, each of the first control signal VIN1 and the second control signal VIN2 is a non-overlap pulse, and the first control signal VIN1 has a narrower pulse width than the second control signal VIN2.
At an initial state, in a state in which the first control signal VIN1 is a low level and the second control signal VIN2 is a high level, the first capacitor C1 is charged with an external supply voltage level, and then, when the first control signal VIN1 and the second control signal VIN2 become a high level, a voltage of 0 V is outputted by the output terminal.
Then, when the first control signal VIN1 is shifted from a high level to a low level and the second control signal VIN2 is shifted from a high level to a low level, a voltage charged in the first capacitor C1 is added to the external supply voltage VDD that is supplied through an inverter IV, and a voltage of about VDD*2 is outputted to the output terminal so as to generate voltage pumping.
However, in the conventional elevated voltage generating apparatus, if the level of the external supply voltage VDD is increased, the pumping voltage is also increased. Therefore, an amount of consumed current is increased in proportion to the external supply voltage at the time of a pumping operation.
FIG. 3 is a graph illustrating an increase in an amount of consumed current due to an increase in supply voltage in the conventional elevated voltage generating apparatus.
As shown in FIG. 3, an amount of consumed current during the pumping operation is increased in proportion to an increase in an external supply voltage level.
As such, if an amount of consumed current is increased, a pumping voltage level exceeds a desired level, and thus the applied stress becomes stronger in memory cells or peripheral elements, thereby causing elements to fail. As a result, the reliability and yield are lowered.